Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.

The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more.

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Foundry and Advanced Packaging team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for a Principal Engineer for Technology and Foundry Interface to join the team.

The candidate for this position will be expected and able to complete the following responsibilities:

• Lead technical interactions with external foundries both in pre-silicon design and post silicon development as well as continuous improvement for Yield and performance during production manufacturing stage to ensure Best-in-class Microsoft first-party and second-party silicon.
• Compile and analyze data using common statistical techniques and effectively present key results along with recommended actions; practice continuous improvement and yield optimization and analyze products to ensure manufacturability and data sheet compliance
• Define and design engineering structure in testchip for technology interception and enablement including data collection, analysis and model-silicon characterization.
• Provide comprehensive Power, Performance, Area and Cost analysis for technology enablement.

Required Qualifications:

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.

Screening Requirements:

• • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
  • This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Preferred Qualifications:

• 9+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Physics, Computer Engineering, Computer Science, Physics, or related field AND 6+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Physics, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
  • OR Doctorate degree in Electrical Engineering, Physics, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
• 8 + years of experience in semiconductor process development and manufacturing.
• 5+ years of experience in technology evaluation, testchip and modeling
• Deep understanding of device physics, foundry design collateral management, process qualification, broad fabrication process experience, device reliability, statistical analysis, yield improvement, and physical failure analysis techniques
• Experience in supporting design teams with PDKs, IP development, tapeout, establishing DFM and design for reliability requirements and implementation of test structures for test chips

• Presentation and communication skills.
• Product yield/performance analysis, and design process co-optimization.

• Familiarity with device-level measurements and associated test equipment, data analysis, modeling, simulation, targeting and projection

• Model based problem solving skills through data analysis and understanding of SOC design features, fab process interactions and test methodology.
• Knowledge of EDA tools from Cadence, Caliber, Synopsys, Siemens for device and IP study.
• Experience in leading cross functional teams and program/project management.
• Probability and statistics background including DOE’s.
• Experience in product and test engineering, and ATE test program methodologies
• Knowledge in digital design floor planning, STA; taking RTL to GDS and optimize for PPA

• Some experience in coding using various languages including but not limited to Python, Java and C++; Leveraging and designing/optimizing AI/ML; DFT and DFM techniques

#SCHIE #CSME

Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $139,900 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay

This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.