Sr. Hardware Design Eng

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Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission.

The Data Processing Unit (DPU) team brings together state-of-the-art software and hardware expertise to create a highly programmable and high-performance ASIC with the capability to efficiently handle large data streams. Thanks to its integrated design, this solution empowers teams to operate with increased agility and deliver significantly superior performance compared to CPU-based alternatives

Central to our mission is development of platforms for Azure Datacenters based on our highly programmable data processing chip (DPU). As a Hardware Board Design Engineer, you will be responsible for the design & development of hardware platforms that shall be used for various applications like Storage, Compute & AI.

#DPU

#SCHIE

#azurehwjobs

Required Qualifications

• 8+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
• Experience in any of the Schematics Design & PCB CAD tools like Cadence Orcad, Altium Designer, Mentor Graphics PADS & Cadence Allegro
• Working experience on high-speed interfaces like PCIe/CXL, DDR, USB, UFS, SERDES…Etc
• Clarity on Signal & Power Integrity concepts
• Experience working in lab environment and using different equipment like DSO, Power supplies, BERT & Traffic generators

Other Qualifications

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications

• 11+ years technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
• Experience working with CM/ODM, Fault isolation, & RCCAs
• Experience working with Thermal Chamber & Protocol analyzers like PCIe, DDR, USB, UFS, SPI & I3C/I2C
• Familiarity with Scripting languages like Phython/ Perl

• Design & develop high-speed boards based on the architecture specification document and deliver detailed HW functional specification document
• Work with cross-functional teams to review the hardware functional specification document and ensure the design meets all the requirements.
• Work with manufacturing team to review the design and ensure the DFM requirements are met
• Work with Diagnostics & HW Test engineers to review the test plans and ensure there is no test coverage gap
• Thorough testing and validation of hardware products to ensure compliance with specifications, requirements and quality standards.
• Perform root cause analysis and troubleshooting of hardware defects in a timely manner and implement preventive measures for future occurrences